1. Technical Field
This invention relates in general to communication systems and information and data processing systems, and more particularly, to digital phase locked logic circuits for extracting a retiming signal from a received serial data stream.
2. Description of the Prior Art
Phase locked loops (PLLs) are a critical component in many data communication networks. PLLs are used for locally maintaining in remote stations a clock signal that corresponds in frequency and phase to the clock of data signals transmitted through the network and received by the station. The difference between a VCO generated signal and the clock signal recovered from the received data is monitored and the phase and frequency of the VCO signal is adapted and "locked" to that of the received data signal.
Progress in increasing performance, speed, reliability, and the simultaneous reduction in size and cost of integrated circuits (LSI and VLSI) continues to create strong interest in the implementation of PLLs in the digital domain. Aside from the obvious advantages associated with digital systems, a digital version of the PLL (DPLL) alleviates some of the problems associated with its analog counterpart; namely, sensitivity to noise and parameter variations, difficulties encountered in building higher order loops, and, depending on the system, the need for initial calibration and periodic adjustments. Various digital phase locked logic circuits are described in the literature. An early survey is given in an article by W. C. Lindsey et al., entitled "Survey of Digital Phase Locked Loops", Proceedings of the IEEE, Vol. 69, No. 4, April 1981, pp. 410-431.
Data jitter (a valid transition occurring other than where expected) and noise (an invalid transition) can be major problems in high speed data communication links. One approach to addressing these problems with DPLL circuit design is described by E. A. Zurfluh in U.S. Pat. No. 4,677,648, entitled "Digital Phase Locked Loop Synchronizer," assigned to the same assignee as the present invention. According to the patent, a local oscillator clock signal of a given frequency is furnished to an analog delay chain which is used in a dual function, i.e., for determining the phase offset between a data signal and a locally generated clock signal, and for obtaining a phase shifted signal. Evaluation means, upon occurrence of a data signal transition, obtains bi-level tap signal values as a phase offset indication and generates an appropriate phase selection signal which selects one of the delay line tap signals as the output clock signal. The evaluation means, which instantaneously corrects the output clock signal on every data edge transition, typically includes an encoder and a look-up table. Although somewhat successful under jitter conditions, the Zurfluh technique experiences difficulty in differentiating between noise and valid data transitions, especially in a high jitter environment.
The DPLL clock extractor described herein, therefore, is designed to address and expand upon the performance limitations of existing digital data retiming circuit technology, and in particular, to allow for higher accuracy in data retiming under high jitter and/or high noise conditions.